Advances in the semiconductor industry continue to provide smaller device geometries. As geometries have been reduced, some failure mechanisms have become more pronounced. One of the most significant contributors to device failure in sub-micron range devices is hot carrier injection (HCI). HCI is an effect where high-energy charges are injected into the gate dielectric of a FET device, and may become lodged in the dielectric. Trapped charges may accumulate over time and affect both the turn-on voltage and the drain current of transistors, and may eventually lead to degraded operation of the device over time.
Carrier injection is a function of field strength between the source and drain of a transistor. Field strength is a function of the physical distance and voltage difference between source and drain channels. The reduction in geometries of semiconductor devices has therefore been accompanied by a reduction in the operating voltage of the device. Many logic devices that operated at 5 volts a number of years ago now operate at 3.3 volts or less.
Thus, in many modern integrated circuits, the core circuitry generally operates at a lower voltage than the I/O circuits. This provides a core circuitry design that operates at higher speeds with lower power consumption. However, since the maximum operating voltage of such core circuitry designs is also lower, these devices may not be used directly with currently known I/O circuits without special design considerations. In particular, stress on the I/O circuits must be taken into consideration and accounted for, otherwise, due to degradation from HCI over time, operation of the device can be negatively impacted.
Therefore, further development in I/O circuits is needed.